Altera: 14nm Stratix and 20nm Arria FPGA details
Altera has revealed more of its next-generation Stratix FPGAs, made on Intel’s 14nm finfet (‘tri-gate’) process, and 20nm TSMC-fabricated Arria FPGAs.
The families will be called Stratix 10 and Arria 10.
For the same power, Stratix 10 will deliver 1.4-1.6x performance compared with existing Stratix V parts, and double the performance is available for 1.3x power.
“You can port an existing design. To get the full 2x performance, you will have to do some re-designing for the new architecture,” said Altera v-p of corporate strategy Danny Biran, who is not yet revealing details of the architecture changes.
The firm also claims the newer Stratix can offer the same performance for 0.3x of the power compared with Stratix V, but, said Biran: “if you just want to maintain performance as today, the mid-range Arria 10 will probably give you a better solution.” – According to him the planar TSMC process costs less than the Intel’s finfet, and Arria 10 will be 15% faster than Stratix V.
“Anything you can do today with Stratix V today you can do with Arria 10 with lower power consumption,” said Biran.
Stratix 10 will also come with 56Gbit/s transceivers, up to four million logic elements, and up to 10x the DSP performance – 10Tflop single precision – through improves MAC (multiply-accumulate) resources.
For the first time, Stratix will get hard processors, of which Altera refuses to say more except it will be a “3rd-generation processor system”.
The die will be ’3D capable’, meaning that the die pin-out and signals are fully defined for 2.5D silicon interposer hybrids. Interposers are expected to be used to combine the FPGAs with SRAM or DRAM where a lot of memory bandwidth is required, or to combine FPGAs with special purpose asics.
Over with Arria 10, Biran is predicting up to a 1.9x performance boost over Altera’s current FPGA+processor combinations, 4x I/O bandwidth and 3x system performance – defined as: 16 28.05Gbit/s transceivers (“already demonstrated on a test chip”), 17.4Gbit/s backplane support, 2.666Gbit/s DDR4 interfacing, and up to 15Gbit/s for Hybrid Memory Cube. And power is 40% down.
They get a “second-generation processor system”, said the firm, which is actually a 1.5GHz dual-core ARM Cortex-A9 with 512kbyte L2 cache, and up to one million look-up tables. “First-generation”, inside Cyclone V and Arria V, was an 800MHz dual-core A9.
Tools are already available for Arria 10.
“Early access customers are currently using the Quartus II software for Generation 10 product development,” said Altera. “Generation 10 devices are supported by tools for higher level design flows that include an OpenCL software development kit [SDK], SoC embedded design suite, and DSP Builder.”
An 8x improvement in compilation times versus the previous generation is claimed, through algorithms that split across multiple cores.
Initial Arria 10 samples are planned for early 2014, and Stratix 10 test chips this year (Quartus II is supporting Stratix 10 in 2014, said the firm).
Courtesy of: Steve Bush